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Espressif Systems /ESP32-S2 /PCNT /INT_ST

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Interpret as INT_ST

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CNT_THR_EVENT_U0)CNT_THR_EVENT_U0 0 (CNT_THR_EVENT_U1)CNT_THR_EVENT_U1 0 (CNT_THR_EVENT_U2)CNT_THR_EVENT_U2 0 (CNT_THR_EVENT_U3)CNT_THR_EVENT_U3

Description

Interrupt status register

Fields

CNT_THR_EVENT_U0

The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
CNT_THR_EVENT_U1

The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
CNT_THR_EVENT_U2

The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
CNT_THR_EVENT_U3

The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data